Virtual Prototyping with SystemC
Today's companies have to deal with complex hardware architectures, e.g. heterogenous multi-core systems which are used in the context of autonomous systems. Moreover, they have a constant pressure to de-liver their products quickly because of many competitors on the market. The old-established design-flow procedures have a performance problem due to the high complexity of modern systems. New development tools and approaches for elec-tronic system level design are needed to fulfil these requirements. In the past the software was developed after the hardware as available. To decrease the time-to-market, costs and efforts, it is necessary to develop software and hardware more concurrently and a support of the collaboration of the hardware and the software developer teams is mandatory. An effective approach for this issue is Virtual Prototyping.
Virtual prototypes are high-speed, fully functional software models of physical hardware systems which can model a complete electronic systems with reasonable simulation speed. Moreover, it is easier to continuously test the product in a so called virtual Hardware in the Loop (vHIL), because the virtual prototype provides visibility and controllability. There are helpful and powerful debugging mechanisms for virtual prototypes which are almost unthinkable on a real hardware system. This leads to a higher quality of the product and a lower supporting effort.
The state-of-the-art modelling language for electronic system level design is SystemC (IEEE Standard 1666). In this seminar we will cover the main concepts of SystemC and Transaction Level Modeling (TLM), and how these concepts can be used practically. The contents are supported by practical hands-on exercises to strengthen understanding. The seminar can be tailored to your actual needs and knowledge level.