Conference and Trade Fair / March 09, 2020 - March 13, 2020
DATE 2020 - Design, Automation and Test in Europe Conference
The “DATE 2020 - Design, Automation and Test in Europe Conference 2020” will take place virtually this year due to the current developments regarding the Corona virus. The date for this is still being determined.
More Information can be found at this link.
Fraunhofer IESE will be represented at DATE 2020 with the presentation "FAST AND ACCURATE DRAM SIMULATION: CAN WE FURTHER ACCELERATE IT? The event is one of the most important European events, consisting of a conference with invited speakers, thematic sessions, tutorials and workshops.
The "DATE 2020" event is one of the most important European events in the field of Embedded Systems and consists of a conference with invited lectures, thematic sessions, tutorials, and workshops.
Fraunhofer IESE will also participate with a lecture:
FAST AND ACCURATE DRAM SIMULATION: CAN WE FURTHER ACCELERATE IT?
Wednesday, 10 March 2020, Dr. Matthias Jung
Virtual platforms are state-of-the-art for design space exploration and simulation of today's complex Systems on Chips (SoCs). The challenge of these virtual platforms is to find the right trade-off between speed and accuracy. For the simulation of Dynamic Random Access Memories (DRAMs), which have complex timing and power behavior, high-accuracy models are needed. However, cycle-accurate DRAM models take up a huge portion of the overall simulation time. Therefore, it is important to accelerate DRAM simulation models while maintaining accuracy. In the literature, different approaches to accelerating the speed of DRAM simulations on virtual platforms already do exist. This paper proposes two new performance optimized DRAM models that further accelerate the simulation speed with merely a negligible degradation in accuracy. The first model is an enhanced Transaction Level Model (TLM), which uses a look-up table to accelerate simulation parts with high bandwidth usage for online scenarios. The other one is a neural-network-based simulator for offline trace analysis. We will show a mathematical methodology for generating the inputs for the look-up table and the optimal artificial training set for the neural network. The TLM model is up to ~5 times faster than a state-of-the-art TLM DRAM simulator. The neural network is able to speed up to~10x, while inferring on a GPU. Both solutions provide only a slight decrease in accuracy, approximately 5%.