DRAMSys: Tool for Optimizing Memory Systems through Simulation Analyses

DRAMSys4.0 is a flexible, fast, and open-source DRAM subsystem design space exploration framework based on SystemC TLM-2.0. It was developed at the Microelectronic Systems Design Research Group of the Technical University of Kaiserslautern and Fraunhofer IESE in order to tackle the challenges of today’s memory systems with respect to applications, performance, power, temperature, retention errors, and different DRAM architectures.

DRAMSys consists of models that reflect the DRAM functionality, power, and temperature. With these models, system designers are able to analyze the limiting parameters and issues with respect to current DRAM standards in their system context.

For this purpose, the framework provides a user-friendly Trace Analyzer tool for deep analysis and insights. With these valuable insights, the designer can optimize the DRAM subsystem with respect to the controller architecture, power and thermal management, as well as device selection and channel configuration for a specific application.

 

© Fraunhofer IESE
DRAMSys Screenshot Trace Analyzer
© Fraunhofer IESE
The DRAMSys Trace Analyzer helps to examine the behavior of an application with respect to its DRAM accesses. This includes, e.g., bank level parallelism and command and data bus load.
DRAMSys Screenshot Trace Analyzer Metrics
© Fraunhofer IESE
The Trace Analyzer offers a Python interface in order to calculate and visualize different metrics based on the simulation data. These include, for example, metrics such as average access latency, bandwidth, or accesses per activate.
DRAMSys thermal analyses
© Fraunhofer IESE
With DRAMSys, it is also possible to perform thermal analyses with the help of the open-source tools DRAMPower and 3D-ICE. Here you can see an example of a smartphone with Wide I/O DRAM, where DRAMSys was used to investigate different refresh strategies.

DRAMSys4.0 features at a glance:

  • TLM2.0-AT-compliant
  • Support for DDR3, DDR4, DDR5*, LPDDR4, LPDDR5* Wide I/O 1/2, GDDR5, GDDR5X GDDR6, and HBM2
  • Scheduling Policies (FIFO, FR-FCFS and FR-FCFS with read/write grouping)
  • Page Policies (open, closed, open adaptive and closed adaptive)
  • Refresh schemes (all-bank refresh, per-bank refresh, pulled-in, postpone)
  • Power-Down modes (PDNA, PDNP, SREF, …)
  • Power Estimation
  • Thermal Simulation
  • Trace Analyzer for visual and metric-based result analysis

* Currently under development.

DRAMSys uses simulation to replace assumptions with facts

DRAMSys will help you explore the design space of the DRAM subsystem to replace your gut feeling with evidence obtained by simulations.

The use cases are manifold and include, among others:

  • Which DRAM configuration/standard fits best to my system?
  • How will new standards like DDR5 or LPDDR5 change the behavior of my system – do they bring any new benefit for my system?
  • How should I configure the memory controller to gain the maximum performance or minimal energy consumption?
  • How can I optimize my system application with respect to the DRAM subsystem used?
 

Introductory presentation on DRAMSys

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Authors: Lukas Steiner, Matthias Jung, Fe­lipe Salerno Prado, Kir­ill Bykov and Nor­bert When

At the SAMOS 2020 Conference, Lukas Steiner explains the basics of DRAMSys. He talks about the special TLM2.0 technology and points out the benefits of DRAMSys compared to traditional simulators.

Further information about DRAM and DRAMSys

Software

Open-Source Version

The open-source version of DRAMSys is hosted on github. The repository is updated regularly with new functions.

Video

DRAMSys3.0 Thermal Simulation

Temperature measurement of a smartphone with Wide I/O DRAM and use of DRAMSys to investigate different refresh strategies.

Research project

MEMTONOMY

Optimizing memory for advanced driver assistance systems and autonomous driving. Fraunhofer aims to close research gap with the participation of Bosch and TU Kaiserslautern.

Publications

  • DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator
    L. Steiner, M. Jung, F. S. Prado, K. Bykov, and N. Wehn Springer LNCS International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2020, Samos Island, Greece.
    To the publication

  • TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
    M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.

  • DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework
    M. Jung, C. Weis, N. Wehn. IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015.