DRAMSys4.0 is a flexible, fast, and open-source DRAM subsystem design space exploration framework based on SystemC TLM-2.0. It was developed at the Microelectronic Systems Design Research Group of the Technical University of Kaiserslautern and Fraunhofer IESE in order to tackle the challenges of today’s memory systems with respect to applications, performance, power, temperature, retention errors, and different DRAM architectures.
DRAMSys consists of models that reflect the DRAM functionality, power, and temperature. With these models, system designers are able to analyze the limiting parameters and issues with respect to current DRAM standards in their system context.
For this purpose, the framework provides a user-friendly Trace Analyzer tool for deep analysis and insights. With these valuable insights, the designer can optimize the DRAM subsystem with respect to the controller architecture, power and thermal management, as well as device selection and channel configuration for a specific application.